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ltc1665/ltc1660 1 166560fa block diagram features description micropower octal 8-bit and 10-bit dacs the 8-bit ltc ? 1665 and 10-bit ltc1660 integrate eight accurate, serially addressable digital-to-analog convert- ers (dacs) in tiny 16-pin narrow ssop packages. each buffered dac draws just 56a total supply current, yet is capable of supplying dc output currents in excess of 5ma and reliably driving capacitive loads to 1000pf. sleep mode further reduces total supply current to 1a. linear technologys proprietary, inherently monotonic volt- age interpolation architecture provides excellent linearity while allowing for an exceptionally small external form factor. ultralow supply current, power-saving sleep mode and extremely compact size make the ltc1665 and ltc1660 ideal for battery-powered applications, while their ease of use, high performance and wide supply range make them excellent choices as general purpose converters. ltc1665 differential nonlinearity (dnl) ltc1660 differential nonlinearity (dnl) applications n tiny: 8 dacs in the board space of an so-8 n micropower: 56a per dac plus 1a sleep mode for extended battery life n pin compatible 8-bit ltc1665 and 10-bit ltc1660 n wide 2.7v to 5.5v supply range n rail-to-rail voltage outputs drive 1000pf n reference range includes supply for ratiometric 0v-to-v cc output n reference input impedance is constant? eliminates external buffer n mobile communications n remote industrial devices n automatic calibration for manufacturing n portable battery-powered instruments n trim/adjust applications l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. 2 15 1 gnd v out a v out b v out c v out d ref cs/ld sck v cc v out h v out g v out f v out e clr d out d in 166560 bd 16 dac a dac h 3 14 dac b dac g 4 13 dac c dac f 5 7 6 8 10 11 9 12 dac d dac e address decoder control logic shift register code 0 64 128 192 255 lsb 166560 g09 0.5 0.4 0.3 0.2 0.1 0 C0.1 C0.2 C0.3 C0.4 C0.5 v cc = 5v v ref = 4.096v code 0 256 512 768 1023 lsb 166560 g13 1 0.8 0.6 0.4 0.2 0 C0.2 C0.4 C0.6 C0.8 C1 v cc = 5v v ref = 4.096v
ltc1665/ltc1660 2 166560fa 1 2 3 4 5 6 7 8 top view gn package 16-lead plastic ssop n package 16-lead pdip 16 15 14 13 12 11 10 9 gnd v out a v out b v out c v out d ref cs/ld sck v cc v out h v out g v out f v out e clr d out d in t jmax = 125c, ja = 150c/w (gn) t jmax = 125c, ja = 100c/w (n) absolute maximum ratings v cc to gnd ............................................... C0.2v to 7.5v logic inputs to gnd ................................. C0.2v to 7.5v v out a , v out b , v out h , ref to gnd .................................C0.2v to (v cc + 0.2v) maximum junction temperature .......................... 125c operating temperature range ltc1665c/ltc1660c .............................. 0c to 70c ltc1665i/ltc1660i ............................ C40c to 85c storage temperature range ................. C65c to 150c lead temperature (soldering, 10 sec) .................. 300c (note 1) pin configuration order information lead free finish tape and reel part marking* package description temperature range ltc1665cgn#pbf ltc1665cgn#pbf 1665 16-lead plastic ssop 0c to 70c ltc1665ign#pbf ltc1665ign#pbf 1665i 16-lead plastic ssop C40c to 85c ltc1660cgn#pbf ltc1660cgn#pbf 1660 16-lead plastic ssop 0c to 70c ltc1660ign#pbf ltc1660ign#pbf 1660i 16-lead plastic ssop C40c to 85c ltc1665cn#pbf ltc1665cn#pbf ltc1665cn 16-lead plastic pdip 0c to 70c ltc1665in#pbf ltc1665in#pbf ltc1665in 16-lead plastic pdip C40c to 85c ltc1660cn#pbf ltc1660cn#pbf ltc1660cn 16-lead plastic pdip 0c to 70c ltc1660in#pbf ltc1660in#pbf ltc1660in 16-lead plastic pdip C40c to 85c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a la bel on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ltc1665/ltc1660 3 166560fa electrical characteristics the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = 2.7v to 5.5v, v ref v cc , v out unloaded, unless otherwise noted. the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = 2.7v to 5.5v, v ref v cc , v out unloaded, unless otherwise noted. symbol p arameter conditions ltc1665 ltc1660 units min typ max min typ max accuracy resolution l 8 10 bits monotonicity v ref v cc C 0.1v (note 2) l 8 10 bits dnl differential nonlinearity v ref v cc C 0.1v (note 2) l 0.1 0.5 0.2 0.75 lsb inl integral nonlinearity v ref v cc C 0.1v (note 2) l 0.2 1.0 0.6 2.5 lsb v os offset error (note 7) l 10 30 10 30 mv v os temperature coefficient l 15 15 v/c fse full-scale error v cc = 5v, v ref = 4.096v l 1 4 3 15 lsb full-scale error temperature coefficient l 30 30 v/c psr power supply rejection v ref = 2.5v 0.045 0.18 lsb/v symbol parameter conditions min typ max units reference input input voltage range l 0v cc v resistance not in sleep mode l 35 65 k capacitance (note 6) 15 pf i ref reference current sleep mode l 0.001 1 a power supply v cc positive supply voltage for specified performance l 2.7 5.5 v i cc supply current v cc = 5v (note 3) v cc = 3v (note 3) sleep mode (note 3) l l l 450 340 1 730 530 3 a a a dc performance short-circuit current low v out = 0v, v cc = 5.5v, v ref = 5.1v, code = full scale l 10 30 100 ma short-circuit current high v out = v cc = 5.5v, v ref = 5.1v, code = 0 l 10 27 120 ma ac performance voltage output slew rate rising (notes 4, 5) falling (notes 4, 5) 0.60 0.25 v/s v/s voltage output settling time to 0.5lsb (notes 4, 5) 30 s capacitive load driving 1000 pf digital i/o v ih digital input high voltage v cc = 2.7v to 5.5v v cc = 2.7v to 3.6v l l 2.4 2.0 v v v il digital input low voltage v cc = 4.5v to 5.5v v cc = 2.7v to 5.5v l l 0.8 0.6 v v v oh digital output high voltage i out = C1ma, d out only l v cc C 1 v v ol digital output low voltage i out = 1ma, d out only l 0.4 v i lk digital input leakage v in = gnd to v cc l 10 a c in digital input capacitance (note 6) l 10 pf
ltc1665/ltc1660 4 166560fa timing characteristics the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (see figure 1) symbol parameter conditions min typ max units v cc = 4.5v to 5.5v t 1 d in valid to sck setup l 40 ns t 2 d in valid to sck hold l 0n s t 3 sck high time (note 6) l 30 ns t 4 sck low time (note 6) l 30 ns t 5 cs/ld pulse width (note 6) l 80 ns t 6 lsb sck high to cs/ld high (note 6) l 30 ns t 7 cs/ld low to sck high (note 6) l 80 ns t 8 d out propagation delay c load = 15pf (note 6) l 58 0n s t 9 sck low to cs/ld low (note 6) l 20 ns t 10 clr pulse width (note 6) l 100 ns t 11 cs /ld high to sck positive edge (note 6) l 30 ns sck frequency continuous square wave (note 6) continuous 23% duty cycle pulse (note 6) gated square wave (note 6) l l l 5.00 7.69 16.7 mhz mhz mhz v cc = 2.7v to 5.5v t 1 d in valid to sck setup (note 6) l 60 ns t 2 d in valid to sck hold (note 6) l 0n s t 3 sck high time (note 6) l 50 ns t 4 sck low time (note 6) l 50 ns t 5 cs/ld pulse width (note 6) l 100 ns t 6 lsb sck high to cs/ld high (note 6) l 50 ns t 7 cs/ld low to sck high (note 6) l 100 ns t 8 d out propagation delay c load = 15pf (note 6) l 5 150 ns t 9 sck low to cs/ld low (note 6) l 30 ns t 10 clr pulse width (note 6) l 120 ns t 11 cs /ld high to sck positive edge (note 6) l 30 ns sck frequency continuous square wave (note 6) continuous 28% duty cycle pulse gated square wave l l l 3.85 5.55 10 mhz mhz mhz note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: nonlinearity and monotonicity are defined from code 4 to code 255 for the ltc1665 and from code 20 to code 1023 for the ltc1660. see applications information. note 3: digital inputs at 0v or v cc . note 4: load is 10k in parallel with 100pf. note 5: v cc = v ref = 5v. dac switched between 0.1v fs and 0.9v fs , i.e., codes 26 and 230 for the ltc1665 or codes 102 and 922 for the ltc1660. note 6: guaranteed by design and not production tested. note 7: measured at code 4 for the ltc1665 and code 20 for the ltc1660.
ltc1665/ltc1660 5 166560fa typical performance characteristics minimum v out vs load current (output sinking) large-signal step response supply current vs temperature supply current vs logic input voltage midscale output voltage vs load current midscale output voltage vs load current minimum supply headroom vs load current (output sourcing) (ltc1665/ltc1660) i out (ma) C30 C20 C10 0 10 20 30 v out (v) 166560 g01 3 2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2 v cc = 4.5v v cc = 5v v cc = 5.5v v ref = v cc code = 128 (ltc1665) code = 512 (ltc1660) sink source i out (ma) C15 C 4 C8 C12 0 4 8 12 15 v out (v) 166560 g02 2 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 v cc = 2.7v v cc = 3v v cc = 3.6v v ref = v cc code = 128 (ltc1665) code = 512 (ltc1660) sink source 0246810 v cc C v out (mv) 166560 g03 1400 1200 1000 800 600 400 200 0 C55c 25c 125c v ref = 4.096v v out < 1lsb code = 255 (ltc1665) code = 1023 (ltc1660) | i out | (ma) (sourcing) | i out | (ma) (sinking) 0246810 v out (mv) 166560 g04 1400 1200 1000 800 600 400 200 0 C55c 25c 125c v cc = 5v code = 0 time (s) 0 20406080100 v out (v) 166560 g05 5 4 3 2 1 0 10% to 90% step v cc = v ref = 5v temperature (c) C55 C35 C15 5 25 45 65 85 105 125 supply current (a) 166560 g06 500 480 460 440 420 400 380 360 340 320 300 v cc = 5.5v v cc = 4.5v v cc = 3.6v v cc = 2.7v logic input voltage (v) 012345 supply current (ma) 166560 g07 2 1.6 1.2 0.8 0.4 0 all digital inputs shorted together
ltc1665/ltc1660 6 166560fa load regulation vs output current load regulation vs output current integral nonlinearity (inl) differential nonlinearity (dnl) typical performance characteristics (ltc1665) code 0 64 128 192 255 lsb 1665/60 g08 1 0.8 0.6 0.4 0.2 0 C0.2 C0.4 C0.6 C0.8 C1 v cc = 5v v ref = 4.096v code 0 64 128 192 255 lsb 166560 g09 0.5 0.4 0.3 0.2 0.1 0 C0.1 C0.2 C0.3 C0.4 C0.5 v cc = 5v v ref = 4.096v i out (ma) C2 C1 0 1 2 v out (lsb) 0.5 0.25 0 C0.25 C0.5 166560 g10 v cc = v ref = 5v code = 128 sink source i out (a) C500 0 500 v out (lsb) 0.5 0.25 0 C0.25 C0.5 166560 g11 sink source v cc = v ref = 3v code = 128
ltc1665/ltc1660 7 166560fa load regulation vs output current load regulation vs output current integral nonlinearity (inl) differential nonlinearity (dnl) typical performance characteristics (ltc1660) code 0 256 512 768 1023 lsb 166560 g12 2.5 2.0 1.5 1.0 0.5 0 C 0.5 C1.0 C1.5 C 2.0 C 2.5 v cc = 5v v ref = 4.096v code 0 256 512 768 1023 lsb 166560 g13 1 0.8 0.6 0.4 0.2 0 C0.2 C0.4 C0.6 C0.8 C1 v cc = 5v v ref = 4.096v i out (ma) C2 C1 0 1 2 v out (lsb) 2 1.5 1 0.5 0 C0.5 C1 C1.5 C2 166560 g14 v cc = v ref = 5v code = 512 sink source i out (a) C500 0 500 v out (lsb) 2 1.5 1 0.5 0 C0.5 C1 C1.5 C2 166560 g15 sink source v cc = v ref = 3v code = 512
ltc1665/ltc1660 8 166560fa block diagram pin functions gnd (pin 1): system ground. v out a to v out h (pins 2-5 and 12-15): dac analog volt- age outputs. the output range is 0to 255 256 ? ? ? ? ? ? v ref for the ltc1665 0to 1023 1024 ? ? ? ? ? ? v ref for the ltc1660 ref (pin 6): reference voltage input. 0v v ref v cc . cs/ld (pin 7): serial interface chip select/load input. when cs/ld is low, sck is enabled for shifting data on d in into the register. when cs/ld is pulled high, sck is disabled and data is loaded from the shift register into the specified dac register(s), updating the analog output(s). cmos and ttl compatible. sck (pin 8): serial interface clock input. cmos and ttl compatible. d in (pin 9): serial interface data input. data on the d in pin is shifted into the 16-bit register on the rising edge of sck. cmos and ttl compatible. d out (pin 10): serial interface data output. data appears on d out 16 positive sck edges after being applied to d in . may be tied to d in of another ltc1665/ltc1660 for daisy- chain operation. cmos and ttl compatible. clr (pin 11): asynchronous clear input. all internal shift and dac registers are cleared to zero at the falling edge of the clr signal, forcing the analog outputs to zero scale. cmos and ttl compatible. v cc (pin 16): supply voltage input. 2.7v v cc 5.5v. (ltc1665/ltc1660) 2 15 1gnd v out a v out b v out c v out d ref cs/ld sck v cc v out h v out g v out f v out e clr d out d in 166560 bd 16 dac a dac h 3 14 dac b dac g 4 13 dac c dac f 5 7 6 8 10 11 9 12 dac d dac e address decoder control logic shift register
ltc1665/ltc1660 9 166560fa timing diagram d in d out c s/ld sck a3 a3 a3 a2 a2 x1 a1 x0 166560 f01 a1 x1 x0 t 2 t 8 t 9 t 11 t 5 t 7 t 6 t 1 t 3 t 4 figure 1 operation transfer function the transfer function is: v out(ideal) = k 256 ? ? ? ? ? ? v ref for the ltc1665 v out(ideal) = k 1024 ? ? ? ? ? ? v ref for the ltc1660 where k is the decimal equivalent of the binary dac input code and v ref is the voltage at ref (pin 6). power-on reset the ltc1665 clears the outputs to zero scale when power is first applied, making system initialization consistent and repeatable. power supply sequencing the voltage at ref (pin 6) should be kept within the range C 0.2v v ref v cc + 0.2v (see absolute maximum rat- ings). particular care should be taken to observe these limits during power supply turn-on and turn-off sequences, when the voltage at v cc (pin 16) is in transition. serial interface referring to figure 2a (2b): with cs/ld held low, data on the d in input is shifted into the 16-bit shift register on the positive edge of sck . the 4-bit dac address, a3-a0, is loaded first (see table 2), then the 8-bit (10-bit) input code, d7-d0 (d9-d0), ordered msb-to-lsb in each case. four (two) dont-care bits, x3-x0 (x1-x0), are loaded last. when the full 16-bit input word has been shifted in, cs/ld is pulled high, loading the dac register with the word and causing the addressed dac output(s) to update. the clock is disabled internally when cs/ld is high. note: sck must be low before cs/ld is pulled low. the buffered serial output of the shift register is available on the d out pin, which swings from gnd to v cc . data appears on d out 16 positive sck edges after being ap- plied to d in . multiple ltc1665/ltc1660s can be controlled from a single 3-wire serial port (i.e., sck, d in and cs /ld) by using the included daisy-chain facility. a series of m chips is configured by connecting each d out (except the last) to d in of the next chip, forming a single 16m-bit shift register. the sck and cs /ld signals are common to all chips in the chain. in use, cs /ld is held low while m 16-bit words are clocked to d in of the first chip; cs /ld is then pulled high, updating all of them simultaneously.
ltc1665/ltc1660 10 166560fa operation sleep mode dac address 1110 b is reserved for the special sleep instruc- tion (see table 2). in this mode, the digital interface stays active while the analog circuits are disabled; static power consumption is thus virtually eliminated. the reference input and analog outputs are set in a high impedance state and all dac settings are retained in memory so that when sleep mode is exited, the outputs of dacs not updated by the wake command are restored to their last active state. d in d out sck c s/ld a3 a2 input word w 0 input code a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 x3 x2 x1 x0 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 x3 x2 x1 x0 a3 166560 f02a 1615 14 13 12 11 10 9 8 7 6 5 4 3 2 1 (enable clk) (update output) address/control dont care input word w 0 input word w C1 d in d out sck c s/ld a3 a2 input word w 0 input code dont care a1 a0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x1 x0 a3 a2 a1 a0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x1 x0 a3 166560 f02b 1615 14 13 12 11 10 9 8 7 6 5 4 3 2 1 (enable clk) (update output) address/control input word w 0 input word w C1 figure 2a. ltc1665 register loading sequence figure 2b. ltc1660 register loading sequence table 1a. ltc1665 input word table 1b. ltc1660 input word a3 a2 a1 address/control a0 d9 d8 d7 d6 d5 d4 d3 d2 d1 x1 x0d0 input code dont care a3 a2 a1 address/control a0 d7 d6 d5 d4 d3 d2 d1 d0 x3 x1 x0x2 dont care input code
ltc1665/ltc1660 11 166560fa operation table 2. dac address/control functions address/control dac status sleep status a3 a2 a1 a0 0 0 0 0 no change wake 0 0 0 1 load dac a wake 0 0 1 0 load dac b wake 0011 load dac c wake 0100 load dac d wake 0101 load dac e wake 0110 load dac f wake 0111 load dac g wake 1000 load dac h wake 1001 no c hange wake 1010 no c hange wake 1011 no c hange wake 1100 no c hange wake 1101 no c hange wake 1110 no c hange sleep 1111 load all dacs with same 8/10-bit code wake sleep mode is initiated by performing a load sequence to address 1110 b (the dac input word d7-d0 [d9-d0] is ignored). once in sleep mode, a load sequence to any other address (including no change addresses 0000 b and 1001-1101 b ) causes the ltc1665/ltc1660 to wake. it is possible to keep one or more chips of a daisy chain in continuous sleep mode by giving the sleep instruction to these chips each time the active chips in the chain are updated. voltage outputs each of the eight rail-to-rail output amplifiers contained in these parts can source or sink up to 5ma. the outputs swing to within a few millivolts of either supply rail when unloaded and have an equivalent output resistance of 85 when driving a load to the rails. the output amplifiers are stable driving capacitive loads up to 1000pf. a small resistor placed in series with the output can be used to achieve stability for any load capacitance. a 1f load can be successfully driven by inserting a 20 resis- tor; a 2.2f load needs only a 10 resistor. in either case, larger values of resistance, capacitance or both may be safely substituted for the values given. rail-to-rail output considerations in any rail-to-rail output voltage dac, the output is limited to voltages within the supply range. if the dac offset is negative, the output for the lowest codes limits at 0v as shown in figure 3b. similarly, limiting can occur near full scale when the ref pin is tied to v cc . if v ref = v cc and the dac full-scale error (fse) is positive, the output for the highest codes limits at v cc as shown in figure 3c. no full-scale limiting can occur if v ref is less than v cc C fse. offset and linearity are defined and tested over the region of the dac transfer function where no output limiting can occur.
ltc1665/ltc1660 12 166560fa operation 166560 f03 input code (b) output voltage negative offset 0v 128 0 255 input code output voltage (a) v ref = v cc v ref = v cc (c) input code output voltage positive fse figure 3. effects of rail-to-rail operation on a dac transfer curve. (a) overall transfer function (b) effect of negative offset for codes near zero scale (c) effect of positive full-scale error for input codes near full scale when v ref = v cc
ltc1665/ltc1660 13 166560fa typical applications a low power quad trim circuit with coarse/fine adjustment v out4 v out1 v out3 v out2 r1 coarse r1 coarse 0.1f 0.1f r1 4 1 2 3 11 3.3v 3.3v r1 coarse r1 r2 r2 r2 fine r2 fine r2 fine r1 coarse r2 fine 166560 ta01 2 15 1 gnd v out a v out b v out c v out d ref cs/ld sck 3-wire serial interface v cc v out h v out g v out f v out e clr to other ltc1665s d out d in 16 dac a dac h 3 14 dac b dac g 4 13 dac c dac f 5 7 6 8 11 9 12 dac d dac e address decoder control logic shift register 0.1f 0.1f 3.3v 1 4 2 u1 ltc1665 C + u2a lt ? 1491 7 6 5 C + u2b lt1491 ltc1258-2.5 0.1f 0.1f r1 14 13 12 r2 C + u2d lt1491 0.1f r1 8 9 10 r2 C + u2c lt1491 r2 >> r1 v out 1 = v out a + example: for r1 = 110 and r2 = 11k, v out 1 = v out a + 0.01 v out b r1 r2 v out b similarly v out 2 , v out 3 , v out 4 10
ltc1665/ltc1660 14 166560fa typical applications an 8-channel bipolar output voltage circuit configuration v out d 5v 5v r r 166560 ta04 2 15 1 gnd v out a v out b v out c v out d ref cs/ld clk 3-wire serial interface v cc v out h v out g v out f v out e clr d out d in 16 dac a dac h 3 14 dac b dac g 4 13 dac c dac f 5 7 6 8 10 11 9 12 dac d dac e address decoder control logic shift register u1 ltc1660 14 13 12 C + u2d lt1491 v out c 5v r r 8 9 10 C + u2c lt1491 v out b 5v r r 7 6 5 C + u2b lt1491 v out a 5v r 0.1f 0.1f v s + v s C r 1 2 4 11 3 C + u2a lt1491 0.1f v out e 5v 14 13 12 C + u3d lt1491 v out f 5v 8 9 10 C + u3c lt1491 v out g 5v 7 6 5 C + u3b lt1491 v out h 5v r 0.1f 0.1f v s + v s C r r r r r r r 1 2 4 11 3 C + u3a lt1491 code 0 512 1023 v out x C5v 0v +4.99v
ltc1665/ltc1660 15 166560fa package description gn package 16-lead plastic ssop (narrow 0.150) (ltc dwg #05-08-1641) please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. gn16 (ssop) 0204 12 3 4 5 6 7 8 .229 C .244 (5.817 C 6.198) .150 C .157** (3.810 C 3.988) 16 15 14 13 .189 C .196* (4.801 C 4.978) 12 11 10 9 .016 C .050 (0.406 C 1.270) .015 .004 (0.38 0.10) w 45 s 0 C 8 typ .007 C .0098 (0.178 C 0.249) .0532 C .0688 (1.35 C 1.75) .008 C .012 (0.203 C 0.305) typ .004 C .0098 (0.102 C 0.249) .0250 (0.635) bsc .009 (0.229) ref .254 min recommended solder pad layout .150 C .165 .0250 bsc .0165 .0015 .045 .005 * dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale
ltc1665/ltc1660 16 166560fa package description please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. n16 rev i 0711 .255 .015* (6.477 0.381) .770* (19.558) max 16 1 2 3 4 5 6 7 8 910 11 12 13 14 15 .020 (0.508) min .120 (3.048) min .130 .005 (3.302 0.127) .065 (1.651) typ .045 C .065 (1.143 C 1.651) .018 .003 (0.457 0.076) .008 C .015 (0.203 C 0.381) .300 C .325 (7.620 C 8.255) .325 +.035 C.015 +0.889 C0.381 8.255 note: 1. dimensions are inches millimeters *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 inch (0.254mm) .100 (2.54) bsc n package 16-lead pdip (narrow .300 inch) (reference ltc dwg # 05-08-1510 rev i)
ltc1665/ltc1660 17 166560fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 1/12 removed typical values in timing characteristics 3, 4
ltc1665/ltc1660 18 166560fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com linear technology corporation 1999 lt 0112 rev a ? printed in usa related parts typical application part number description comments ltc1661 dual 10-bit v out dac in 8-lead msop package v cc = 2.7v to 5.5v micropower rail-to-rail output ltc1663 single 10-bit v out dac in sot-23 package v cc = 2.7v to 5.5v, internal reference, 60a ltc1446/ ltc1446l dual 12-bit v out dacs in so-8 package with internal reference ltc1446: v cc = 4.5v to 5.5v, v out = 0v to 4.095v ltc1446l: v cc = 2.7v to 5.5v, v out = 0v to 2.5v ltc1448 dual 12-bit v out dac in so-8 package v cc = 2.7v to 5.5v, external reference can be tied to v cc ltc1454/ ltc1454l dual 12-bit v out dacs in so-16 package with added functionality ltc1454: v cc = 4.5v to 5.5v, v out = 0v to 4.095v ltc1454l: v cc = 2.7v to 5.5v, v out = 0v to 2.5v ltc1458/ ltc1458l quad 12-bit rail-to-rail output dacs with added functionality ltc1458: v cc = 4.5v to 5.5v, v out = 0v to 4.095v ltc1458l: v cc = 2.7v to 5.5v, v out = 0v to 2.5v ltc1590 dual 12-bit i out dac in so-16 package v cc = 4.5v to 5.5v, 4-quadrant multiplication ltc1659 single rail-to-rail 12-bit v out dac in 8-lead msop package v cc : 2.7v to 5.5v low power multiplying v out dac. output swings from gnd to ref. ref input can be tied to v cc lt1460 micropower precision series reference, 2.5v, 5v, 10v versions 0.075% max, 10ppm/c max, only 130a supply current 2 6 16 11 dac a clr v cc ref 5v u1 ltc1660 0.1f 0.1f 0.1f v a 3 v h = v h + v h v l = v l + v l v l 1 2 v h (from main dac) v l (from main dac) 10v C5v r g 50k r f 5k v b v c v d gnd 166560 ta03 3 dac b 0.1f r g 50k r g 50k r g 50k C + u2a lt1369 quad 0.1f 5 7 6 r f 5k r f 5k r f 5k logic drive pin driver (1 of 2) dac c dac d dac h dac g dac f dac e cs/ld sck d in 4 5 8 1 9 7 C + u2b lt1369 quad v l v out v h code a 512 512 512 code b 1023 512 0 v h , v l C 250mv 0 + 250mv v a = v c = 2.5v for resistor values shown: adjustment range = 250mv adjustment step size = 500v note: dacs e through h can be con?gured for a second pin driver with u2c and u2d of the lt1369 v h = v h + (v a C v b ) r f r g v l = v l + (v c C v d ) r f r g v h a pin driver v h and v l adjustment circuit for ate applications

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